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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:16:23 08/19/2014 
-- Design Name: 
-- Module Name:    CombinationLogic1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity CombinationLogic1 is
    Port ( clk_in_dummy : in  STD_LOGIC;
           ce_in_dummy : in  STD_LOGIC;
           in1 : in  STD_LOGIC;
           in2 : in  STD_LOGIC;
           out1 : out  std_logic_vector(1 downto 0));
end CombinationLogic1;

architecture Behavioral of CombinationLogic1 is
signal locOut1     : std_logic;
signal locOut2     : std_logic;
begin

locOut1 <= '1' when (in1 = '1' and in2 = '1') else '0' ;
locOut2 <= '1' when (in1 = '1' and in2 = '0') else '0' ;

out1 <= locOut1 & locOut2;

end Behavioral;

